CS501 Advance Computer Architecture solved Mid term past paper fall 28 November 2011

Q.1 consider the following sequence of instruction going through the SRC pipeline  (5)

200: shl r6, r3, 2

204: str r3, 32

208: sub r2, r4, r5

212: add r1. R2, r3

216: ld r7, 48

What hazards can occur executing above instructions and how can be resolved these?

Solution:

There is a data hazard between instruction three and four (208 , 212).

For more detail please consult lecture # 20. topic: SRC hazard detection and correction

 Q.2 arranges the following according to control signal for pipeline stages.

·         Decode and operand read

·         Register Writeback

·         ALU Operation

·         Memory Access

·         Instruction fetch

Solution:

1.       Instruction fetch

2.       Decode and operand read

3.       ALU Operation

4.       Memory Access

5.       Register Writeback

Q.3 write structural RTL for the following instruction. (3)

In ra, c2

Solution:

Q.4 write structural RTL for the following instruction. (3)

Jump [ra+c2]

Solution:

Q.5  write the simple form of the given structural RTL . (2)

Solution:

Sub ra, rb rc

Q.6 what is the difference between latency and throughput?

Solution:

Latency is defined as the time required to process a single instruction, while throughput is

defined as the number of instructions processed per second. Pipelining cannot lower the

latency of a single instruction; however, it does increase the throughput. With respect to

the example discussed earlier, in a non-pipelined machine there would be one instruction

processed after an average of 5 cycles, while in a pipelined machine, instructions are

completed after each and every cycle (in the steady-state, of course!!!). Hence, the overall

time required to execute the program is reduced.

1. SRC instruction set type B have  --------- instructions.

                                                               i.      2

                                                            ii.      3

                                                            iii.      4

                                                           iv.      5             

2. ----------- is defined as the time required to process a single instruction

                                                               i.      Latency & throughput

                                                            ii.      Latency

                                                            iii.      Throughput

                                                           iv.      None

3. A  scalar processor that can issue multiple instructions simultaneously is said to be --------

                                                              i.      Superscalar

                                                            ii.      Multiscalar

                                                          iii.      ---

                                                          iv.      ---

4. Which memory is faster than Cache?

                                                              i.      RAM

                                                            ii.      Processor Registers

                                                          iii.      Primary memory

                                                          iv.      Secondary memory

5. In ---------  we discussed that a number of instructions are executed in a staggered fashion.

                                                              i.      Parallel processing

                                                            ii.      Multiprocessing

                                                          iii.      Pipelining

                                                          iv.      Multithreading