CS501 5 Advance Computer Architecture assignment solution fall 2012

Question No. 1

According to the Radix conversion algorithm, convert 492₁₀ to base 16 (Write down all the steps which are involved in conversion).

Answer:

492/16 =30( rem=12), x0=12=C

30/16= 1(rem=14), x1=14=E, x2=1

Thus 49210=1EC16

Question No. 2

According to the Radix conversion algorithm, convert the hexadecimal number D4₁₆ to base 10 (Write down all the steps which are involved in conversion).

Answer:

X=0

X= x+D (=13) =13

X=16*13+4= 212

Hence D416=21210

CS501 4 Advanced Computer Architecture assignment solution fall january 2012

Question No.1

Consider a floppy drive having a transfer rate of 48 KB per second is attached to a 32 bit, 10MIPS CPU using an interrupt driven interface. The drive has 16-bit data bus.

Suppose that the interrupt overhead is 10 instructions. Calculate the fraction of CPU time required to service this drive when it is active.

Solution:

Since the floppy drive has a 16-bit data bus, it can transfer two bytes at one time.

Thus its transfer rate is 48/2 = 24 K half-words (16-bits each) per second.

This corresponds to an overhead of 10 instructions or 24K x 10 = 24 x 2³ x 10 = 240000 instructions per second.

Question No.2

A hard disk with 10 platters has 512 tracks per platter, 512 sectors per track and 512 bytes/sector. What is the total capacity of the disk?

Solution:

512 bytes x 512

Sectors=0.25MB/track

0.25MB x 512 tracks=0.125GB/platter

Therefore the hard disk has the total capacity of 10 x 0.125=1.25GB

Question No.3

How many platters are required for an 80GB disk if there are 2048 bytes/sector, 2048 sectors per track and 2048 tracks per platter?

Solution:

The capacity of one platter

= 2048 x 2048 x 2048

= 8GB

For an 80GB hard disk, we need 80/8

= 10 such platters.

CS501 3 Advanced Computer Architecture Assignment solution fall december 2011

Question No.1:

Let us consider an I/O bus that can transfer 6 bytes of data in one bus cycle. presume that a designer is considering to attach the following two components to this bus:

Hard drive with a transfer rate of 80 M bytes/sec

Video card with a transfer rate of 200 M bytes/sec

What will be the implications if both of these components need to work simultaneously?

(The maximum frequency of the bus is 30 MHz)

Solution:

 The maximum frequency of the bus is 30 MHz. This means that the maximum bandwidth of this bus is 30 x 6 = 180 Mbytes/sec. Now, the demand for bandwidth from these two components will be 80 + 200 =280 Mbytes/sec which is more than the 180 Mbytes/sec that the bus can provide.

Thus, if the designer uses these two components with this bus, one or both of these components will be operating at reduced bandwidth.

Question No.2:

If a bus requires 15 nsec for bus requests, 10 nsec for arbitration and the average time to complete an operation is 10 nsec after the access to the bus has been granted, is it possible for such a bus to perform 40 million IOPS?

Solution:

For 40 million IOPS, the average time for each IOP is 1 / (40 x 10⁶) =25 nsec. Given the

information about the bus, the sum of the three times is 10 + 10 + 15 = 35 nsec for a

complete I/O operation. This means that the bus can perform a maximum of 1 / ( 35 x 10^-9 ) = 28.6 million IOPS.

Thus, it will not be able to perform 40 million IOPS.

CS501 Advance Computer Architecture solved Mid term past paper fall 28 November 2011

Q.1 consider the following sequence of instruction going through the SRC pipeline  (5)

200: shl r6, r3, 2

204: str r3, 32

208: sub r2, r4, r5

212: add r1. R2, r3

216: ld r7, 48

What hazards can occur executing above instructions and how can be resolved these?

Solution:

There is a data hazard between instruction three and four (208 , 212).

For more detail please consult lecture # 20. topic: SRC hazard detection and correction

 Q.2 arranges the following according to control signal for pipeline stages.

·         Decode and operand read

·         Register Writeback

·         ALU Operation

·         Memory Access

·         Instruction fetch

Solution:

1.       Instruction fetch

2.       Decode and operand read

3.       ALU Operation

4.       Memory Access

5.       Register Writeback

Q.3 write structural RTL for the following instruction. (3)

In ra, c2

Solution:

Q.4 write structural RTL for the following instruction. (3)

Jump [ra+c2]

Solution:

Q.5  write the simple form of the given structural RTL . (2)

Solution:

Sub ra, rb rc

Q.6 what is the difference between latency and throughput?

Solution:

Latency is defined as the time required to process a single instruction, while throughput is

defined as the number of instructions processed per second. Pipelining cannot lower the

latency of a single instruction; however, it does increase the throughput. With respect to

the example discussed earlier, in a non-pipelined machine there would be one instruction

processed after an average of 5 cycles, while in a pipelined machine, instructions are

completed after each and every cycle (in the steady-state, of course!!!). Hence, the overall

time required to execute the program is reduced.

1. SRC instruction set type B have  --------- instructions.

                                                               i.      2

                                                            ii.      3

                                                            iii.      4

                                                           iv.      5             

2. ----------- is defined as the time required to process a single instruction

                                                               i.      Latency & throughput

                                                            ii.      Latency

                                                            iii.      Throughput

                                                           iv.      None

3. A  scalar processor that can issue multiple instructions simultaneously is said to be --------

                                                              i.      Superscalar

                                                            ii.      Multiscalar

                                                          iii.      ---

                                                          iv.      ---

4. Which memory is faster than Cache?

                                                              i.      RAM

                                                            ii.      Processor Registers

                                                          iii.      Primary memory

                                                          iv.      Secondary memory

5. In ---------  we discussed that a number of instructions are executed in a staggered fashion.

                                                              i.      Parallel processing

                                                            ii.      Multiprocessing

                                                          iii.      Pipelining

                                                          iv.      Multithreading

CS501 2 Advance Computer Architecture fall 2011 assignment solution

Question No. 1:

Find the execution time for a program that executes 60 million instructions on a processor with an average CPI of 1.0 and a clock period of 33.3 nsec.

Execution time = IC * CPI * T

IC = 60 * 10 ⁶

CPI = 1.0

T = 33.3 nsec  = 33.3 * 10^-9

Execution time = 60 * 10 ⁶ * 1.0 * 33.3 * 10^-9

= 1.998

Question No. 2:

Consider a program that executes 200 million instructions in 10 seconds. What is the MIPS rating for this program?

MIPS = IC / ( ET * 10⁶ )

IC = 200 millions

ET = 10 sec

MIPS = 200 millions / (10 * 10⁶)

MIPS = 20

cs501 assignment no 1 solution fall 2011

	Assignment No. 01 Semester Fall 2011 Advance Computer Architecture - CS501			Total Marks: 20 Due Date: 31/10/2011
Objective: To learn and understand classification of instructions. Instructions: Please read the following instructions carefully before solving & submitting assignment: Assignment should be in your own wordings not copied from net, handouts or books. It should be clear that your assignment will not get any credit (zero marks) if: o        The assignment is submitted after due date. o        The submitted assignment does not open or file is corrupt. o        The assignment is copied (from other student or copied from handouts or internet). GOOD LUCK
Question No 1			Marks: 5+5+5+5 = 20
Write the code to implement the expression A = (B+C) * (D + E) for 1)      3-address instructions 2)      2-address instructions 3)      1-address instructions 4)      0-address instructions In accordance with programming language practice, computing the expression should not change the values of its operands. ========================================================================= Solution 1)      3-address instructions add x, b, c add y, d, e mul a, x, y 2)      2-address instructions  load r, d                                                    add r, e  load y, b        add y, c                                             mul y, r                                                    store a, y 3)      1-address instructions lda B adda C sta x lda D adda E mula x sta A 4)      0-address instructions push b                                                    push c add push d                                                    push e           add mul                                                    pop a